OCV (On-Chip Variation) analysis methodology has been used to cover the process variation effect on timing analysis in the IC design implementation stage. Any circuit design is assigned one or more timing specifications. Because the switching time for a transistor depends on the actual length and width of its channel, process variations that affect the gate dimensions also affect timing. To ensure that an IC can meet its performance specifications in the presence of process variations, on-chip variation (OCV) analysis has been used to include timing margin in the design. A typical OCV analysis assumed that process variations caused the channel length of each transistor to assume its worst case value. As a result, a large margin was included in the time budget of the circuit, to accommodate the variations.
This worst-case OCV analysis has an accuracy issue, because the probability of every device having its worst case maximum time is not very high. Also, in a cell having a large number of devices, some of the variations cancel each other out. Thus, assuming that every device has its worst case maximum delay value may cause difficulty in meeting the design performance and schedule requirements, due to overly inaccurate and pessimistic timing analysis.
Stage-Based OCV analysis attempts to resolve the inaccuracy issue of traditional OCV methodology. U.S. Patent Application Publication No. 2005/0081171 is incorporated by reference herein. This publication describes a method in which the number of gate stages of a circuit path are determined. As the number of stages increases, the OCV delay becomes a smaller fraction of the total path delay. A derating factor is determined as a function of the number of gate stages. The time budget for the circuit path is then reduced to account for the derating factor.
The stage based OCV method still provides a pessimistic margin, making it difficult to achieve design performance and schedule requirements.